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`timescale 1ns / 1ps

module Edge_Detect#(
parameter INIT = 1'b1
)(
input i_Clk,		//input Clk
input i_Rst_n,		//Global rst,Active Low
input i_Signal,

output O_Signal_Edge		//Output Signal
);

reg  r_Signal_a;
reg  r_Signal_b;

wire w_Signal_Pos;
wire w_Signal_Neg;

always@(posedge i_Clk or negedge i_Rst_n)
begin
    if(~i_Rst_n)
    begin
        r_Signal_a <= INIT;
        r_Signal_b <= INIT;
    end
    else
    begin
        r_Signal_a <= i_Signal;
        r_Signal_b <= r_Signal_a;
    end
end

assign w_Signal_Pos = r_Signal_a && !r_Signal_b;
assign w_Signal_Neg = !r_Signal_a && r_Signal_b;

assign O_Signal_Edge = (INIT) ? w_Signal_Pos : w_Signal_Neg;

endmodule
